Content Addressable Memory (CAM) circuits use semiconductor memory components such as Static Random Access Memory (SRAM) circuits forming memory cells and additional comparison circuitry that permits any required searches to be completed in a single clock cycle. Searches using Content Addressable Memory circuits and associated comparison circuitry are typically faster than algorithmic searches. Because Content Addressable Memory circuits are faster, they are often used in Internet routers for complicated address look-up functions. They are also used in database accelerators, data compression applications, neural networks, Translation Look-aside Buffers (TLB) and processor caches.
In a content addressable memory circuit, any data is typically stored randomly in different memory locations, which are selected by an address bus. Data is also typically written directly into a first entry or memory location. Each memory location could have associated with the memory a pair of special status bits that keep track of whether the memory location includes valid data or is empty and available for overriding. Any information stored at a specific memory location is located by comparing every bit in memory with any data placed in a comparand register. A match flag is asserted to allow a user to know that the data is in memory. Priority encoders sort the matching locations by priority and make address matching location available to a user.
As compared to more standard memory address circuits, in a Content Addressable Memory circuit, data is supplied and an address obtained, and thus, address lines are not required. A router address look-up search examines a destination address for incoming packets and examines the address look-up table to find an appropriate output port. This algorithm and circuitry involves longest-prefix matching and uses the Internet Protocol (IP) networking standard in most cases.
Current routing tables have about 30,000 entries or more and the number of entries is increasing rapidly. Terabit-class routers perform hundreds of millions of searches per second and update routing tables thousands of times per second. Because of present and future projected routing requirements, Content Addressable Memory circuits are used to complete a search in a single cycle. In these circuits, comparison circuitry is usually added to every CAM memory cell, forming a parallel look-up engine. The CAM memory cells can be arranged in horizontal words, such as four horizontal words that are each five bits long, for example. The memory cells contain both storage and comparison circuitry. Search lines run vertically and broadcast search data to the CAM memory cells. Match lines run horizontally across the array and indicate whether a search data matches the word in the row. An activated match line indicates a match, and a deactivated match line indicates a non-match or mismatch. The match lines are input to the priority encoder, which generates an address corresponding to a match location.
Typically, a search will begin by precharging high all match lines in a matched state. Data is broadcast by drivers onto search lines. The CAM cells compare the stored bit against a bit on corresponding search lines. Any cells that match data do not affect match lines, but any cells with a mismatch would pull-down a match line for any word that has at least one mismatch. Other match lines are activated and pre-charged high.
The priority encoder will generate a search address location for any matching data. For example, an encoder could select numerically the smallest numbered match line for two activated match lines and generate a match address, for example 01. This can be input to a RAM that contains output ports. The match address output is a pointer that retrieves associated data from RAM. An SRAM cell could include positive feedback in a back-to-back inverter with two access transistors connecting bit lines to storage nodes under control of a word line. Data is written or read into and from a cell through the bit lines. Mismatches occur quite often and typically only a small number of matches occur, and the circuit function results in high power consumption on match lines.
The circuit can be arrayed to handle a number of binary divisible row locations. A column structure can be hierarchical in nature. In a CAM circuit, it is sometimes necessary to encode one or more row locations. Because only one location can typically be encoded at a time, the locations are prioritized and the highest priorities are encoded. The priority can be set based on a physical order. Devices made from CAM circuits also typically require a physical prioritization. Usually a priority encoder is done with many stages of combinational logic.
In commonly assigned U.S. Pat. No. 6,678,184, the disclosure which is hereby incorporated by reference in its entirety, the CAM circuit has a reduced semiconductor substrate area to provide an increase in performance and improves packing density to make router designs smaller and more efficient. The reduction of substrate area is accomplished by the unique placement, organization, and interconnection of transistors in the CAM circuit. As disclosed, the CAM circuit is in a semiconductor substrate and includes a match signal output having a logical state set to a first value. The compare circuit compares a stored data value to an input compare data value having an enable input. A matched output is coupled to the matched signal output and a compare data input is coupled to a compare data signal and a stored data input. If the enable input receives an enable true signal and a stored data input receives a stored data signal, and the compare data false input receives a compare data signal, then the logical state of the matched signal output changes to a second value to indicate no match. As also disclosed, a first data storage device stores the data value having first and second word lines, first and second bitlines, a stored data output, and a first conductive strip electrically coupling the stored data output to the stored data input of the compare circuit. The stored data output provides the stored data signal. The first word line of the first data storage device is formed in a first conductive region and a second word line of the first data storage device is formed physically separate and distinct from the first conductive region in a second conductive region. The second data storage device has a memory cell storing an enable value having first and second word lines, first and second bitlines, and an enable output. A second conductive strip electrically couples the enable output to the enable input of the compare circuit. The enable output provides the enable true signal.
Although this design provides for an increase in performance and improves the packing density of the CAM circuit, the memory cell stability is not robust. Alpha or similar atomic particles can cause shorts and memory cell instability.